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[VHDL-FPGA-Verilogbahe

Description: 设计四 拔河游戏机 1、 设计一个能进行拔河游戏的电路。 2、 电路使用15个(或9个)发光二极管,开机后只有中间一个发亮,此即拔河的中心点。 3、 游戏双方各持一个按钮,迅速地、不断地按动,产生脉冲,谁按得快,亮点就向谁的方向移动,每按一次,亮点移动一次。 4、 亮点移到任一方终端二极管时,这一方就获胜,此时双方按钮均无作用,输出保持,只有复位后才使亮点恢复到中心。 5、 用数码管显示获胜者的盘数。 教学提示: 1、 按钮信号即输入的脉冲信号,每按一次按钮都应能进行有效的计数。 2、 用可逆计数器的加、减计数输入端分别接受两路脉冲信号,可逆计数器原始输出状态为0000,经译码器输出,使中间一只二极管发亮。 3、 当计数器进行加法计数时,亮点向右移;进行减法计数时,亮点向左移。 4、 由一个控制电路指示谁胜谁负,当亮点移到任一方终端时,由控制电路产生一个信号,使计数器停止计数。 5、 将双方终端二极管“点亮”信号分别接两个计数器的“使能”端,当一方取胜时,相应的计数器进行一次计数,这样得到双方取胜次数的显示。 6、 设置一个“复位”按钮,使亮点回到中心,取胜计数器也要设置一个“复位”按钮,使之能清零。 -design a tug-of-war game, can design a game of tug of war circuit. 2, circuit use 15 (or 9), light-emitting diodes, come only among a shiny, namely, the center of tug-of-war. 3, the game with a two button rapidly and continuously pressed, have a pulse, who by fast, Who bright spots on the move, every time, a bright spot in Mobile. 4, the party moved to highlight terminal diode, on the winning side, this time the two sides had no effect buttons, to maintain output, so after only bright spot reduction restored to the center. 5, digital Display won the bookkeeping. Teaching Tip : one, that the button signal input pulse signal every time the button should be able to effectively counter. 2, with reversible counter, plus or minus count input to receive two pulse signal, reversible counter to the
Platform: | Size: 292864 | Author: 万金油 | Hits:

[MiddleWarelsb

Description: 用verilog语言写的拔河游戏机,配套硬件试验箱-Verilog language used to write the tug-of-war games, matching hardware chamber
Platform: | Size: 8211456 | Author: 周于 | Hits:

[Embeded-SCM DevelopTug-of-war-game

Description: 拔河游戏机制作的原理图PCB原理图。数字逻辑电路。-Tug-of-war game produced by PCB schematic schematic. Digital logic circuits.
Platform: | Size: 78848 | Author: 果冻 | Hits:

[VHDL-FPGA-Verilogbahe

Description: 采用verilog设计的拔河比赛,在QuartusII9。0仿真验证并在DE2上测试过-Using Verilog to design the tug of war, in QuartusII9. 0 simulation and test on DE2
Platform: | Size: 559104 | Author: 王东 | Hits:

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